Cypress SL811HS Bedienungsanleitung

SL811HS Embedded USB Host/Slave ControllerSL811HSCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docum

SL811HSDocument 38-08008 Rev. *D Page 10 of 32Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE regis

SL811HSDocument 38-08008 Rev. *D Page 11 of 32Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h.SOF Counter Hig

SL811HSDocument 38-08008 Rev. *D Page 12 of 32SL811HS Slave Mode RegistersWhen in slave mode, the registers in the SL811HS are dividedinto two major

SL811HSDocument 38-08008 Rev. *D Page 13 of 32Endpoint Control RegistersEndpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Eac

SL811HSDocument 38-08008 Rev. *D Page 14 of 32Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains info

SL811HSDocument 38-08008 Rev. *D Page 15 of 32Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA opera

SL811HSDocument 38-08008 Rev. *D Page 16 of 32Interrupt Enable Register, Address [06h] . The SL811HSprovides an Interrupt Request Output that is acti

SL811HSDocument 38-08008 Rev. *D Page 17 of 32Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each en

SL811HSDocument 38-08008 Rev. *D Page 18 of 32Physical ConnectionsThese parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. Th

SL811HSDocument 38-08008 Rev. *D Page 19 of 32The diagram below illustrates a simple +3.3V voltage source.Package Markings (28-pin PLCC)YYWW = Date c

SL811HSDocument 38-08008 Rev. *D Page 2 of 32Data Port, Microprocessor InterfaceThe SL811HS microprocessor interface provides an 8-bitbidirectional d

SL811HSDocument 38-08008 Rev. *D Page 20 of 3248-Pin TQFP Physical Connections48-Pin TQFP AXC Pin Layout*See Table 35 on page 21 for Pin and Signal D

SL811HSDocument 38-08008 Rev. *D Page 21 of 3248/28-Pin USB Host Controller Pins DescriptionThe SL811HST-AXC is packaged in a 48-pin TQFP. The SL811H

SL811HSDocument 38-08008 Rev. *D Page 22 of 3233 25 BIDIR D6 Data 6. Microprocessor Data/Address Bus.34 – NC NC No connection.35 – NC NC No connectio

SL811HSDocument 38-08008 Rev. *D Page 23 of 32Package Markings (48-Pin TQFP)YYWW = Date codeXXXX = Product codeX.X = Silicon revision number

SL811HSDocument 38-08008 Rev. *D Page 24 of 32Electrical SpecificationsAbsolute Maximum RatingsThis section lists the absolute maximum ratings of the

SL811HSDocument 38-08008 Rev. *D Page 25 of 32DC CharacteristicsUSB Host Transceiver CharacteristicsEvery VDD pin, including USB VDD, must have a dec

SL811HSDocument 38-08008 Rev. *D Page 26 of 32Bus Interface Timing RequirementsI/O Write CycleNote nCS an be held LOW for multiple Write cycles provi

SL811HSDocument 38-08008 Rev. *D Page 27 of 32I/O Read CycleNote nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Tim

SL811HSDocument 38-08008 Rev. *D Page 28 of 32DMA Write CycleNote nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence i

SL811HSDocument 38-08008 Rev. *D Page 29 of 32DMA Read CycleNote Data is held until nDACK goes high regardless of state of nREAD.Reset TimingNote Clo

SL811HSDocument 38-08008 Rev. *D Page 3 of 32PLL Clock GeneratorEither a 12 MHz or a 48 MHz external crystal is used with theSL811HS[1]. Two pins, X1

SL811HSDocument 38-08008 Rev. *D Page 30 of 32Clock Timing SpecificationsOrdering InformationCLK CLOCK TIMINGtrisetfallthightclktlowClock Timin

SL811HSDocument 38-08008 Rev. *D Page 31 of 32© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change withou

SL811HSDocument 38-08008 Rev. *D Page 32 of 32Document History Page Document Title: SL811HS Embedded USB Host/Slave ControllerDocument Number: 38-08

SL811HSDocument 38-08008 Rev. *D Page 4 of 32“SL811HS Slave Mode Registers” on page 12 describes Slaveregister definitions). Access to the registers

SL811HSDocument 38-08008 Rev. *D Page 5 of 32USB-A/USB-B Host Control Registers [Address = 00h, 08h] . Once the other SL811HS Control registers are c

SL811HSDocument 38-08008 Rev. *D Page 6 of 32USB-A/USB-B Host Base Length [Address = 02h, 0Ah]. The USB A/B Host Base Length register contains the ma

SL811HSDocument 38-08008 Rev. *D Page 7 of 32USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register

SL811HSDocument 38-08008 Rev. *D Page 8 of 32Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with

SL811HSDocument 38-08008 Rev. *D Page 9 of 32Interrupt Enable Register [Address = 06h]. The SL811HSprovides an Interrupt Request Output, which is act