Cypress CY14B101L Bedienungsanleitung PDF herunterladen

CY14B101L

1 Mbit (128K x 8) nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-06400 Rev. *I Revised January 30, 2009

Features

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with STK14CA8

■

Hands off automatic STORE on power down with only a small

capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by

software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited READ, WRITE, and RECALL cycles

■

200,000 STORE cycles to QuantumTrap

■

20 year data retention at 55°C

■

Single 3V +20%, –10% operation

■

Commercial and industrial temperature

■

32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages

■

RoHS compliance

Functional Description

The Cypress CY14B101L is a fast static RAM with a nonvolatile

element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent, nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power down. On

power up, data is restored to the SRAM (the RECALL operation)

from the nonvolatile memory. Both the STORE and RECALL

operations are also available under software control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

1024 X 1024

QuantumTrap

1024 x 1024

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 17 18

Inhaltsverzeichnis

Seite 1 - 1 Mbit (128K x 8) nvSRAM

CY14B101L1 Mbit (128K x 8) nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600Document Number: 001-06

Seite 2

CY14B101LDocument Number: 001-06400 Rev. *I Page 10 of 18SRAM Write CycleParameterDescription25 ns 35 ns 45 ns UnitMin Max Min Max Min MaxCypressPar

Seite 3

CY14B101LDocument Number: 001-06400 Rev. *I Page 11 of 18AutoStore or Power Up RECALLParameter Alt DescriptionCY14B101LUnitMin MaxtHRECALL [13]tRESTOR

Seite 4

CY14B101LDocument Number: 001-06400 Rev. *I Page 12 of 18Software Controlled STORE/RECALL CycleThe software controlled STORE/RECALL cycle follows. [16

Seite 5

CY14B101LDocument Number: 001-06400 Rev. *I Page 13 of 18Hardware STORE CycleParameter Alt DescriptionCY14B101LUnitMin MaxtPHSBtHLHXHardware STORE Pul

Seite 6

CY14B101LDocument Number: 001-06400 Rev. *I Page 14 of 18Ordering InformationSpeed(ns)Ordering Code Package Diagram Package TypeOperatingRange25 CY14B

Seite 7

CY14B101LDocument Number: 001-06400 Rev. *I Page 15 of 1845 CY14B101L-SZ45XCT 51-85127 32-pin SOIC CommercialCY14B101L-SZ45XC 51-85127 32-pin SOIC CY

Seite 8

CY14B101LDocument Number: 001-06400 Rev. *I Page 16 of 18Figure 15. 48-Pin Shrunk Small Outline Package (51-85061)Package Diagrams (continued)51-8506

Seite 9

CY14B101LDocument Number: 001-06400 Rev. *I Page 17 of 18Document History PageDocument Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-

Seite 10 - SRAM Write Cycle

Document Number: 001-06400 Rev. *I Revised January 30, 2009 Page 18 of 18AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor

Seite 11 - HRECALL

CY14B101LDocument Number: 001-06400 Rev. *I Page 2 of 18PinoutsFigure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOPPin DefinitionsPin Name Alt IO Type

Seite 12 - CY14B101L

CY14B101LDocument Number: 001-06400 Rev. *I Page 3 of 18Device OperationThe CY14B101L nvSRAM is made up of two functional compo-nents paired in the sa

Seite 13

CY14B101LDocument Number: 001-06400 Rev. *I Page 4 of 18Hardware RECALL (Power Up)During power up or after any low power condition (VCC <VSWITCH),

Seite 14

CY14B101LDocument Number: 001-06400 Rev. *I Page 5 of 18Preventing StoreDisable the AutoStore function by initiating an AutoStore Disablesequence. A s

Seite 15

CY14B101LDocument Number: 001-06400 Rev. *I Page 6 of 18.Table 1. Hardware Mode Selection CE WE OEA15 – A0Mode IO PowerH X X X Not Selected Output Hi

Seite 16 - 51-85061-*C

CY14B101LDocument Number: 001-06400 Rev. *I Page 7 of 18Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. These user

Seite 17

CY14B101LDocument Number: 001-06400 Rev. *I Page 8 of 18Data Retention and EnduranceParameter Description Min UnitDATARData Retention at 55°C20YearsNV

Seite 18 - PSoC Solutions

CY14B101LDocument Number: 001-06400 Rev. *I Page 9 of 18AC Switching Characteristics SRAM Read CycleParameterDescription25 ns 35 ns 45 ns UnitMin Ma