Cypress CY14B101NA Bedienungsanleitung

CY14B101LACY14B101NA1-Mbit (128 K × 8/64 K × 16) nvSRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 10 of 26AC Test ConditionsInput pulse levels...

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 11 of 26AC Switching Characteristics ParametersDescription20 ns 25 ns 45 nsUnitCypressParamet

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 12 of 26Notes22. BHE and BLE are applicable for x16 configuration only.23. WE must be HIGH du

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 13 of 26Figure 9. SRAM Write Cycle #2: CE Controlled[27, 28, 29, 30]Figure 10. SRAM Write C

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 14 of 26AutoStore/Power-Up RECALLParameter Description20 ns 25 ns 45 nsUnitMin Max Min Max Mi

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 15 of 26Software Controlled STORE/RECALL CycleParameter[37, 38]Description20 ns 25 ns 45 nsUn

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 16 of 26Hardware STORE CycleParameter Description20 ns 25 ns 45 nsUnitMin Max Min Max Min Max

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 17 of 26 Notes43. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configurati

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 18 of 26Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOperatingRange20

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 19 of 26Ordering Code DefinitionOption:T - Tape and ReelBlank - Std.Speed:20 - 20 ns25 - 25 n

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 2 of 26Contents1-Mbit (128 K x 8/64 K x 16) nvSRAM ...1Features ..

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 20 of 26Package Diagrams Figure 16. 32-Pin SOIC (51-85127)Figure 17. 44-Pin TSOP II (51-850

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 21 of 26Figure 18. 48-Pin SSOP (51-85061)Package Diagrams (continued)51-85061 *D[+] Feedbac

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 22 of 26Figure 19. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)Package Diagrams (continu

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 23 of 26AcronymsDocument ConventionsUnits of MeasureFigure 20. 54-Pin TSOP II (51-85160)Pack

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 24 of 26Document History Page Document Title: CY14B101LA, CY14B101NA 1-Mbit (128 K × 8/64 K ×

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 25 of 26*C 2733909 GVCH/AESA 07/09/09 Removed 48-ball FBGA package and added 54-pin TSOP II P

Document #: 001-42879 Rev. *K Revised January 18, 2011 Page 26 of 26All products and company names mentioned in this document may be the trademarks

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 3 of 26Pinouts Figure 1. Pin Diagram - 44-Pin TSOP II Figure 2. Pin Diagram - 48-Pin SSOP a

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 4 of 26Figure 3. 48-Ball FBGA and 54-Pin TSOP IITable 1. Pin DefinitionsPin Name I/O Type D

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 5 of 26Device OperationThe CY14B101LA/CY14B101NA nvSRAM is made up of twofunctional component

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 6 of 26SRAM write operations that are in progress when HSB is drivenLOW by any means are give

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 7 of 26Preventing AutoStoreThe AutoStore function is disabled by initiating an AutoStoredisab

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 8 of 26Best PracticesnvSRAM products have been used effectively for over 27 years.While ease-

CY14B101LACY14B101NADocument #: 001-42879 Rev. *K Page 9 of 26Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. The