Cypress CY7C1344H Bedienungsanleitung PDF herunterladen

2-Mbit (64K x 36) Flow-Through Sync SRAM

CY7C1344H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-00211 Rev. *B Revised April 26, 2006

Features

• 64K x 36 common I/O

• 3.3V core power supply

• 3.3V/2.5V I/O supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 8.0 ns (100-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1344H is a 64K x 36 synchronous cache RAM

designed to interface with high-speed microprocessors with

minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

first address in a burst and increments the address automati-

cally for the rest of the burst access. All synchronous inputs

are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC

, ADSP,

and

ADV), Write Enables

(

[A:D]

and BWE

)

, and Global Write (GW

). Asynchronous

inputs include the Output Enable (OE

) and the ZZ pin.

The CY7C1344H allows either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects

an interleaved burst sequence, while a LOW selects a linear

burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP

) or the cache Controller

Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) input.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

The CY7C1344H operates from a +3.3V core power supply

while all outputs may operate with either a +3.3V/2.5V supply.

All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Logic Block Diagram

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

[1:0]

DQP

0, A1, A

ADV

CLK

ADSP

ADSC

BWE

CE1

CE2

CE3

SLEEP

CONTROL

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

[+] Feedback

1 2 3 4 5 6 ... 14 15

Inhaltsverzeichnis

Seite 1 - CY7C1344H

2-Mbit (64K x 36) Flow-Through Sync SRAMCY7C1344HCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Docume

Seite 2

CY7C1344HDocument #: 001-00211 Rev. *B Page 10 of 15Timing DiagramsRead Cycle Timing[16]Note: 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is

Seite 3

CY7C1344HDocument #: 001-00211 Rev. *B Page 11 of 15Write Cycle Timing[16, 17]Note: 17. Full width Write can be initiated by either GW LOW; or by GW H

Seite 4

CY7C1344HDocument #: 001-00211 Rev. *B Page 12 of 15Read/Write Timing[16, 18, 19]Notes: 18. The data bus (Q) remains in High-Z following a Write cycle

Seite 5 - Truth Table

CY7C1344HDocument #: 001-00211 Rev. *B Page 13 of 15ZZ Mode Timing [20, 21]Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descr

Seite 6

CY7C1344HDocument #: 001-00211 Rev. *B Page 14 of 15© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change

Seite 7 - Electrical Characteristics

CY7C1344HDocument #: 001-00211 Rev. *B Page 15 of 15Document History PageDocument Title: CY7C1344H 2-Mbit (64K x 36) Flow-Through Sync SRAMDocument Nu

Seite 8 - Thermal Resistance

CY7C1344HDocument #: 001-00211 Rev. *B Page 2 of 15 Selection Guide133 MHz 100 MHz UnitMaximum Access Time 6.5 8.0 nsMaximum Operating Current 225

Seite 9 - [+] Feedback

CY7C1344HDocument #: 001-00211 Rev. *B Page 3 of 15 Pin Definitions Name I/O DescriptionA0, A1, AInput-SynchronousAddress Inputs used to select one of

Seite 10 - Timing Diagrams

CY7C1344HDocument #: 001-00211 Rev. *B Page 4 of 15Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

Seite 11 - Timing Diagrams (continued)

CY7C1344HDocument #: 001-00211 Rev. *B Page 5 of 15ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min. Max. UnitIDDZZSleep mo

Seite 12

CY7C1344HDocument #: 001-00211 Rev. *B Page 6 of 15Truth Table for Read/Write[2, 3]Function GW BWE BWDBWCBWBBWARead HHXXXXRead HLHHHHWrite Byte (A, DQ

Seite 13

CY7C1344HDocument #: 001-00211 Rev. *B Page 7 of 15Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Stor

Seite 14

CY7C1344HDocument #: 001-00211 Rev. *B Page 8 of 15Capacitance[9]Parameter Description Test Conditions100 TQFP Max. UnitCINInput Capacitance TA = 25°C

Seite 15

CY7C1344HDocument #: 001-00211 Rev. *B Page 9 of 15Switching Characteristics Over the Operating Range[10, 11]Parameter Description133 MHz 100 MHzUnitM

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