Cypress AutoStore STK17T88 Spezifikationen PDF herunterladen (Seite 13)

STK17T88

Document Number: 001-52040 Rev. *C Page 13 of 24

nvSRAM Operation

The STK17T88 nvSRAM is made up of two functional compo-

nents paired in the same physical cell. These are the SRAM

memory cell and a nonvolatile QuantumTrap cell. The SRAM

memory cell operates similar to a standard fast static RAM. Data

in the SRAM can be transferred to the nonvolatile cell (the

STORE operation), or from the nonvolatile cell to SRAM (the

RECALL operation). This unique architecture allows all cells to

be stored and recalled in parallel. During the STORE and

RECALL operations SRAM READ and WRITE operations are

inhibited. The STK17T88 supports unlimited read and writes

similar to a typical SRAM. In addition, it provides unlimited

RECALL operations from the nonvolatile cells and up to 200K

STORE operations.

SRAM READ

The STK17T88 performs a READ cycle whenever E and G are

low while W

and HSB are high. The address specified on pins

0-14

determine which of the 32,768 data bytes are accessed.

When the READ is initiated by an address transition, the outputs

are valid after a delay of t

AVQV

(READ cycle #1). If the READ is

initiated by E

and G, the outputs are valid at t

ELQV

or at t

GLQV

whichever is later (READ cycle #2). The data outputs repeatedly

respond to address changes within the t

AVQV

access time

without the need for transitions on any control input pins, and

remain valid until another address change or until E

or G is

brought high, or W

and HSB is brought low.

Figure 13. AutoStore Mode

SRAM WRITE

A WRITE cycle is performed whenever E and W are low and HSB

is high. The address inputs must be stable prior to entering the

WRITE cycle and must remain stable until either E

or W goes

high at the end of the cycle. The data on the common I/O pins

DQ0-7 are written into memory if it is valid t

DVWH

before the end

of a W

controlled WRITE or t

DVEH

before the end of an E

controlled WRITE.

It is recommended that G

be kept high during the entire WRITE

cycle to avoid data bus contention on common I/O lines. If G

left low, internal circuitry turns off the output buffers t

WLQZ

after

goes low.

AutoStore Operation

The STK17T88 stores data to nvSRAM using one of three

storage operations. These operations are Hardware Store

(activated by HSB

), Software Store (activated by an address

sequence), and AutoStore (on power down).

AutoStore operation, a unique feature of Cypress QuanumTrap

technology that is a standard feature on the STK17T88.

During normal operation, the device draws current from V

charge a capacitor connected to the V

CAP

pin. This stored

charge is used by the chip to perform a single

STORE operation.

If the voltage on the V

pin drops below V

SWITCH

, the part

automatically disconnects the V

CAP

pin from V

. A STORE

operation is initiated with power provided by the V

CAP

capacitor.

Figure 13 shows the proper connection of the storage capacitor

CAP

) for automatic store operation. Refer to the DC

Characteristics (V

= 2.7V-3.6V) table for the size of the

capacitor. The voltage on the V

CAP

pin is driven to 5V by a charge

pump internal to the chip. A pull up should be placed on W

hold it inactive during power up.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware Store operations are ignored unless at least one

WRITE operation has taken place since the most recent

STORE

or RECALL cycle. Software initiated STORE cycles are

performed regardless of whether a WRITE operation has taken

place. The HSB

signal can be monitored by the system to detect

an AutoStore cycle is in progress.

Hardware STORE (HSB) Operation

The STK17T88 provides the HSB pin to control and

acknowledge the

STORE operations. The HSB pin can be used

to request a hardware

STORE cycle. When the HSB pin is driven

low, the STK17T88 conditionally initiates a

STORE operation

after t

DELAY

. An actual STORE cycle only begins if a WRITE to

the SRAM took place since the last

STORE or RECALL cycle.

The HSB

pin has a very resistive pull up and is internally driven

low to indicate a busy condition while the

STORE (initiated by

any means) is in progress. This pin must be externally pulled up

if it is used to drive other inputs.

SRAM READ and WRITE operations that are in progress when

HSB

is driven low by any means are given time to complete

before the STORE operation is initiated. After HSB

goes low, the

STK17T88 continues to allow SRAM operations for t

DELAY

During t

DELAY

, multiple SRAM READ operations may take place.

If a WRITE is in progress when HSB

is pulled low, it is allowed a

time, t

DELAY

, to complete. However, any SRAM WRITE cycles

requested after HSB

goes low are inhibited until HSB returns

high.

During any

STORE operation, regardless of how it was initiated,

the STK17T88 continues to drive the HSB

pin low, releasing it

only when the

STORE is complete. Upon completion of the

STORE operation, the STK17T88 remains disabled until the

HSB

pin returns high.

If HSB

is not used, it should be left unconnected.

Hardware Recall (POWER UP)

During power up or after any low power condition

SWITCH

), an internal RECALL request is latched. When

again exceeds the sense voltage of V

SWITCH

, a RECALL

cycle is automatically initiated and takes t

HRECALL

to complete.

CAP

10k Ohm

0.1µF

CAP

Not Recommended for New Designs

[+] Feedback

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 23 24

STK17T88 10
51-85061-*C 23

Kommentare zu diesen Handbüchern

Keine Kommentare

Cypress AutoStore STK17T88 Spezifikationen Seite 13

Kommentare zu diesen Handbüchern