Cypress CY62157CV33 Bedienungsanleitung PDF herunterladen

512K x 16 Static RAM

CY62157CV30/33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05014 Rev. *F Revised August 31, 2006

Features

• Temperature Ranges

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

• Voltage range:

— CY62157CV30: 2.7V–3.3V

— CY62157CV33: 3.0V–3.6V

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 5.5 mA @ f = f

max

• Low standby power

• Easy memory expansion with CE

, CE

and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Available in Pb-free and non Pb-free 48-ball FBGA

package

Functional Description

[1]

The CY62157CV30/33 are high-performance CMOS static

RAMs organized as 512K words by 16 bits. These devices

feature advanced circuit design to provide ultra-low active

current. This is ideal for providing More Battery Life™

(MoBL™) in portable applications such as cellular telephones.

The devices also have an automatic power-down feature that

significantly reduces power consumption by 80% when

addresses are not toggling. The device can also be put into

standby mode reducing power consumption by more than 99%

when deselected (CE

HIGH or CE

LOW or both BLE and

BHE

are HIGH). The input/output pins (I/O

through I/O

) are

placed in a high-impedance state when: deselected (CE

HIGH or CE

LOW), outputs are disabled (OE HIGH), both

Byte High Enable and Byte Low Enable are disabled (BHE

BLE

HIGH), or during a write operation (CE

LOW and CE

HIGH and WE LOW).

Writing to the device is accomplished by taking Chip Enable 1

(CE

) and Write Enable (WE) inputs LOW and Chip Enable 2

(CE

) HIGH. If Byte Low Enable (BLE) is LOW, then data from

I/O pins (I/O

through I/O

), is written into the location

specified on the address pins (A

through A

). If Byte High

Enable (BHE

) is LOW, then data from I/O pins (I/O

through

I/O

) is written into the location specified on the address pins

through A

Reading from the device is accomplished by taking Chip

Enable 1 (CE

) and Output Enable (OE) LOW and Chip

Enable 2 (CE

) HIGH while forcing the Write Enable (WE)

HIGH. If Byte Low Enable (BLE

) is LOW, then data from the

memory location specified by the address pins will appear on

I/O

to I/O

. If Byte High Enable (BHE) is LOW, then data from

memory will appear on I/O

to I/O

. See the truth table at the

back of this data sheet for a complete description of read and

write modes.

The CY62157CV30/33 are available in a 48-ball FBGA

package.

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Logic Block Diagram

512K × 16

RAM Array

I/O

–I/O

ROW DECODER

COLUMN DECODER

SENSE AMPS

DATA IN DRIVERS

I/O

–I/O

BLE

BHE

Power -down

Circuit

BHE

BLE

[+] Feedback

1 2 3 4 5 6 ... 12 13

Inhaltsverzeichnis

Seite 1 - 512K x 16 Static RAM

512K x 16 Static RAMCY62157CV30/33Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #: 38-05014

Seite 2

CY62157CV30/33Document #: 38-05014 Rev. *F Page 10 of 13Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]Truth TableCE1CE2WE OE BHE BLE Inputs/Outpu

Seite 3 - IL(min.)

CY62157CV30/33Document #: 38-05014 Rev. *F Page 11 of 13Typical DC and AC Characteristics12.010.06.04.008.0 ISB (µA)12.010.06.04.02.02.20.08.0ICC (mA

Seite 4

CY62157CV30/33Document #: 38-05014 Rev. *F Page 12 of 13© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to ch

Seite 5

CY62157CV30/33Document #: 38-05014 Rev. *F Page 13 of 13Document History PageDocument Title: CY62157CV30/33 512K x 16 Static RAMDocument Number: 38-0

Seite 6

CY62157CV30/33Document #: 38-05014 Rev. *F Page 2 of 13 Product PortfolioProduct RangeVCC RangePower DissipationOperating (ICC) mAStandby (ISB2) µAf

Seite 7

CY62157CV30/33Document #: 38-05014 Rev. *F Page 3 of 13Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.

Seite 8

CY62157CV30/33Document #: 38-05014 Rev. *F Page 4 of 13Electrical Characteristics Over the Operating RangeParameter Description Test ConditionsCY6215

Seite 9

CY62157CV30/33Document #: 38-05014 Rev. *F Page 5 of 13Capacitance[7]Parameter Description Test Conditions Max. UnitCINInput Capacitance TA = 25°C, f

Seite 10 - CY62157CV30/33

CY62157CV30/33Document #: 38-05014 Rev. *F Page 6 of 13Switching Characteristics Over the Operating Range[10]Parameter Description70 nsUnitMin. Max.R

Seite 11

CY62157CV30/33Document #: 38-05014 Rev. *F Page 7 of 13 Switching WaveformsRead Cycle No. 1 (Address Transition Controlled)[15, 16]Read Cycle No. 2 (

Seite 12

CY62157CV30/33Document #: 38-05014 Rev. *F Page 8 of 13Write Cycle No. 1 (WE Controlled)[14, 18, 19]Notes: 18. Data I/O is high-impedance if OE = VIH

Seite 13

CY62157CV30/33Document #: 38-05014 Rev. *F Page 9 of 13Write Cycle No. 2 (CE1 or CE2 Controlled) [14, 18, 19]Write Cycle No. 3 (WE Controlled, OE LOW

Verwandte Modelle: CY62157CV30

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