Cypress CY7C1170V18 Bedienungsanleitung PDF herunterladen

CY7C1166V18, CY7C1177V18

CY7C1168V18, CY7C1170V18

18-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06620 Rev. *D Revised March 06, 2008

Features

■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz to 400 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1-compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1166V18 – 2M x 8

CY7C1177V18 – 2M x 9

CY7C1168V18 – 1M x 18

CY7C1170V18 – 512K x 36

Functional Description

The CY7C1166V18, CY7C1177V18, CY7C1168V18, and

CY7C1170V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with an advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of K and K

. Each address location is associated with two 8-bit

words (CY7C1166V18), or 9-bit words (CY7C1177V18), or 18-bit

words (CY7C1168V18), or 36-bit words (CY7C1170V18) that

burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input

(ZQ). Synchronous data outputs (Q, sharing the same physical

pins as the data inputs D) are tightly matched to the two output

echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current 1080 1020 920 850 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 26 27

Inhaltsverzeichnis

Seite 1 - CY7C1168V18, CY7C1170V18

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V1818-Mbit DDR-II+ SRAM 2-Word BurstArchitecture (2.5 Cycle Read Latency)Cypress Semiconductor Corporatio

Seite 2

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 10 of 27Write Cycle DescriptionsThe write cycle descriptions

Seite 3

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 11 of 27The write cycle descriptions of CY7C1170V18 follows.[

Seite 4

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 12 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs in

Seite 5

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 13 of 27IDCODEThe IDCODE instruction causes a vendor-specific

Seite 6

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 14 of 27TAP Controller State DiagramFigure 2 shows the tap co

Seite 7

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 15 of 27TAP Controller Block DiagramFigure 3. Tap Controller

Seite 8

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 16 of 27TAP AC Switching CharacteristicsThe Tap AC Switching

Seite 9

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 17 of 27Identification Register Definitions Instruction Field

Seite 10

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 18 of 27Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit #

Seite 11

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 19 of 27Power Up Sequence in DDR-II+ SRAM DDR-II+ SRAMs must

Seite 12

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 2 of 27Logic Block Diagram (CY7C1166V18)Logic Block Diagram (

Seite 13

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 20 of 27Maximum RatingsExceeding maximum ratings may shorten

Seite 14

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 21 of 27CapacitanceTested initially and after any design or p

Seite 15

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 22 of 27Switching CharacteristicsOver the operating range[20,

Seite 16

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 23 of 27Switching WaveformRead/Write/Deselect SequenceFigure

Seite 17

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 24 of 27Ordering Information Not all of the speed, package an

Seite 18

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 25 of 27333 CY7C1166V18-333BZC 51-85180 165-Ball Fine Pitch B

Seite 19

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 26 of 27Package DiagramFigure 8. 165-Ball FBGA (13 x 15 x 1.4

Seite 20

Document Number: 001-06620 Rev. *D Revised March 06, 2008 Page 27 of 27QDR™ is a trademark of Cypress Semiconductor Corp. QDR RAMs and Quad Data Rate

Seite 21

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 3 of 27Logic Block Diagram (CY7C1168V18)Logic Block Diagram (

Seite 22

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 4 of 27Pin ConfigurationsCY7C1166V18 (2M x 8)165-Ball FBGA (1

Seite 23

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 5 of 27Pin Configurations (continued)CY7C1168V18 (1M x 18)165

Seite 24

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 6 of 27Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]Inpu

Seite 25

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 7 of 27ZQ Input Output Impedance Matching Input. This input i

Seite 26

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 8 of 27Functional OverviewThe CY7C1166V18, CY7C1177V18, CY7C1

Seite 27

CY7C1166V18, CY7C1177V18CY7C1168V18, CY7C1170V18Document Number: 001-06620 Rev. *D Page 9 of 27echo clock and follows the timing of any data pin. Thi

Verwandte Modelle: CY7C1177V18

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Inhaltsverzeichnis

Verwandte Modelle: CY7C1177V18

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