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CY7C024AV/024BV/025AV/026AV

CY7C0241AV/0251AV/036AV

3.3V 4K/8K/16K x 16/18 Dual-Port

Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06052 Rev. *J Revised December 10, 2008

Features

■

True dual-ported memory cells which enable simultaneous

access of the same memory location

■

4, 8 or 16K × 16 organization

■

(CY7C024AV/024BV

[1]

/ 025AV/026AV)

■

4 or 8K × 18 organization (CY7C0241AV/0251AV)

■

16K × 18 organization (CY7C036AV)

■

0.35 micron CMOS for optimum speed and power

■

High speed access: 20 and 25 ns

■

Low operating power

❐

Active: I

= 115 mA (typical)

❐

Standby: I

SB3

= 10 μA (typical)

■

Fully asynchronous operation

■

Automatic power down

■

Expandable data bus to 32 bits, 36 bits or more using Master

and Slave chip select when using more than one device

■

On chip arbitration logic

■

Semaphores included to permit software handshaking

between ports

■

INT flag for port-to-port communication

■

Separate upper byte and lower byte control

■

Pin select for Master or Slave (M/S)

■

Commercial and industrial temperature ranges

■

Available in 100-pin Pb-free TQFP and 100-pin TQFP

Notes

1. CY7C024AV and CY7C024BV are functionally identical.

2. IO

–IO

for x16 devices; IO

–IO

for x18 devices.

3. IO

–IO

for x16 devices; IO

–IO

for x18 devices.

4. A

–A

for 4K devices; A

–A

for 8K devices; A

–A

for 16K devices.

5. BUSY

is an output in master mode and an input in slave mode.

R/W

8/9L

–IO

15/17L

Control

Address

Decode

–A

11/12/13L

R/W

BUSY

Control

Interrupt

Semaphore

Arbitration

SEM

INT

M/S

–IO

7/8L

R/W

8/9L

–IO

15/17R

–IO

7/8R

–A

11/1213L

True Dual-Ported

RAM Array

–A

11/12/13R

R/W

BUSY

SEM

INT

Address

Decode

–A

11/12/13R

[2]

[3]

[5]

12/13/14

8/9

12/13/14

8/9

12/13/14 12/13/14

[4]

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 18 19

Inhaltsverzeichnis

Seite 1 - Static RAM

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AV3.3V 4K/8K/16K x 16/18 Dual-PortStatic RAMCypress Semiconductor Corporation • 198 Champion Court •

Seite 2 - CY7C025AV (8K × 16)

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 10 of 19Data Retention ModeThe CY7C024AV/024BV/025AV/026AV andCY7

Seite 3

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 11 of 19Switching WaveformsNotes29. R/W is HIGH for read cycles.3

Seite 4 - CY7C036AV (16K × 18)

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 12 of 19Notes34. R/W or CE must be HIGH during all address transi

Seite 5 - Interrupts

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 13 of 19Notes43. CE = HIGH for the duration of the above timing (

Seite 6 - Semaphore Operation

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 14 of 19Note47. CEL = CER = LOW.Switching Waveforms (continued)VA

Seite 7

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 15 of 19Note48. If tPS is violated, the busy signal is asserted o

Seite 8

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 16 of 19Notes49. tHA depends on which enable pin (CEL or R/WL) is

Seite 9

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 17 of 19Ordering Information 4K x16 3.3V Asynchronous Dual-P

Seite 10 - CY7C0241AV/0251AV/036AV

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 18 of 19Package DiagramFigure 17. 100-Pin Pb-Free Thin Plastic Q

Seite 11

Document #: 38-06052 Rev. *J Revised December 10, 2008 Page 19 of 19All products and company names mentioned in this document may be the trademarks of

Seite 12

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 2 of 19 Pin ConfigurationsFigure 1. 100-Pin TQFP (Top View)Notes

Seite 13

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 3 of 19Figure 2. 100-Pin TQFP (Top View)Notes8. A12L on the CY7C

Seite 14

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 4 of 19Figure 3. 100-Pin TQFP (Top View)Pin Configurations (cont

Seite 15

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 5 of 19ArchitectureThe CY7C024AV/024BV/025AV/026AV andCY7C0241AV/

Seite 16

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 6 of 193FFF for the CY7C026AV/36AV) is the mailbox for the right

Seite 17

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 7 of 19 Table 1. Non-Contending Read/WriteInputs OutputsOperati

Seite 18

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 8 of 19Maximum RatingsExceeding maximum ratings[14] may shorten t

Seite 19

CY7C024AV/024BV/025AV/026AVCY7C0241AV/0251AV/036AVDocument #: 38-06052 Rev. *J Page 9 of 19Figure 4. AC Test Loads and Waveforms3.0VGND90%90%10%3ns3

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