Cypress CY7C1268V18 Bedienungsanleitung PDF herunterladen (Seite 22)

CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

Document Number: 001-06347 Rev. *D Page 22 of 27

Switching Characteristics

Over the Operating Range

[21, 22]

Cypress

Parameter

Consortium

Parameter

Description

400 MHz 375 MHz 333 MHz 300 MHz

Unit

Min Max Min Max Min Max Min Max

POWER

(Typical) to the first Access

[23]

1–1–1–1–ms

CYC

KHKH

K Clock Cycle Time 2.50 8.4 2.66 8.4 3.0 8.4 3.3 8.4 ns

KHKL

Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – t

CYC

KLKH

Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – t

CYC

KHKH

K Clock Rise to K Clock Rise

(rising edge to rising edge)

1.06–1.13–1.28–1.40– ns

Setup Times

AVKH

Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns

IVKH

Control Setup to K Clock Rise (LD, R/W) 0.4 – 0.4 – 0.4 – 0.4 – ns

SCDDR

IVKH

Double Data Rate Control Setup to Clock

(K, K

) Rise (BWS

, BWS

)

0.28–0.28–0.28–0.28– ns

DVKH

[X:0]

Setup to Clock (K/K) Rise 0.28 – 0.28 – 0.28 – 0.28 – ns

Hold Times

KHAX

Address Hold after K Clock Rise

0.4 – 0.4 – 0.4 – 0.4 – ns

KHIX

Control Hold after K Clock Rise (LD, R/W)

0.4 – 0.4 – 0.4 – 0.4 – ns

HCDDR

KHIX

Double Data Rate Control Hold after Clock

(K/K

) Rise (BWS

, BWS

)

0.28–0.28–0.28–0.28– ns

KHDX

[X:0]

Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – 0.28 – ns

Output Times

CHQV

K/K Clock Rise to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 ns

DOH

CHQX

Data Output Hold after K/K Clock Rise (Active

to Active)

–0.45 – –0.45 – –0.45 – –0.45 – ns

CCQO

CHCQV

K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 ns

CQOH

CHCQX

Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns

CQD

CQHQV

Echo Clock High to Data Valid – 0.2 0.2 0.2 0.2 ns

CQDOH

CQHQX

Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns

CQH

CQHCQL

Output Clock (CQ/CQ) HIGH

[24]

0.81–0.88–1.03–1.15– ns

CQHCQH

CQ Clock Rise to CQ Clock Rise

[24]

(rising edge to rising edge)

0.81–0.88–1.03–1.15– ns

CHZ

CHQZ

Clock (K/K) Rise to High-Z

(Active to High-Z)

[25, 26]

–0.45–0.45–0.45–0.45ns

CLZ

CHQX1

Clock (K/K) Rise to Low-Z

[25, 26]

–0.45 – –0.45 – –0.45 – –0.45 – ns

QVLD

CQHQVLD

Echo Clock High to QVLD Valid

[27]

–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns

DLL Timing

KC Var

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns

KC lock

DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – Cycles

KC Reset

K Static to DLL Reset

[28]

30–30–30–30– ns

Notes

22. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being

operated and outputs data with the output timing of that frequency range.

23. This part has an internal voltage regulator; t

POWER

is the time that the power must be supplied above V

minimum initially before a read or write operation is initiated.

24. These parameters are extrapolated from the input timing parameters (t

KHKH

– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

25. t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of“AC Test Loads and Waveforms” on page 21. Transition is measured ±100 mV from steady-state

voltage.

26. At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than t

27. t

QVLD

spec is applicable for both rising and falling edges of QVLD signal.

28. Hold to >V

or <V

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