Cypress CY7C1312BV18 Bedienungsanleitung PDF herunterladen

18-Mbit QDR™-II SRAM 2-Word

Burst Architecture

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05619 Rev. *F Revised June 2, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1310BV18 – 2M x 8

CY7C1910BV18 – 2M x 9

CY7C1312BV18 – 1M x 18

CY7C1314BV18 – 512K x 36

Functional Description

The CY7C1310BV18, CY7C1910BV18, CY7C1312BV18, and

CY7C1314BV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has data outputs to

support read operations and the write port has data inputs to

support write operations. QDR-II architecture has separate data

inputs and data outputs to completely eliminate the need to

“turn-around” the data bus required with common IO devices.

Access to each port is accomplished through a common address

bus. The read address is latched on the rising edge of the K clock

and the write address is latched on the rising edge of the K

clock.

Accesses to the QDR-II read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are provided with DDR interfaces. Each

address location is associated with two 8-bit words

(CY7C1310BV18), 9-bit words (CY7C1910BV18), 18-bit words

(CY7C1312BV18), or 36-bit words (CY7C1314BV18) that burst

sequentially into or out of the device. Because data can be trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K

and C and C), memory bandwidth is maximized

while simplifying system design by eliminating bus

“turn-arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current x8 735 630 550 mA

x9 735 630 550

x18 800 675 600

x36 900 750 650

[+] Feedback

1 2 3 4 5 6 ... 28 29

Inhaltsverzeichnis

Seite 1 - Burst Architecture

18-Mbit QDR™-II SRAM 2-WordBurst ArchitectureCY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Cypress Semiconductor Corporation • 198 Champion Cour

Seite 2

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 10 of 29Truth TableThe truth table for CY7C1310BV18, CY7C1910BV1

Seite 3

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 11 of 29Write Cycle DescriptionsThe write cycle description tabl

Seite 4

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 12 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incor

Seite 5

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 13 of 29IDCODEThe IDCODE instruction loads a vendor-specific, 32

Seite 6

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 14 of 29TAP Controller State DiagramThe state diagram for the TA

Seite 7

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 15 of 29TAP Controller Block DiagramTAP Electrical Characteristi

Seite 8

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 16 of 29TAP AC Switching Characteristics Over the Operating Rang

Seite 9

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 17 of 29Identification Register Definitions Instruction FieldVal

Seite 10 - CY7C1312BV18, CY7C1314BV18

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 18 of 29Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bu

Seite 11

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 19 of 29Power Up Sequence in QDR-II SRAMQDR-II SRAMs must be pow

Seite 12

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 2 of 29Logic Block Diagram (CY7C1310BV18)Logic Block Diagram (CY

Seite 13

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 20 of 29Maximum RatingsExceeding maximum ratings may impair the

Seite 14

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 21 of 29ISB1Automatic Power Down CurrentMax VDD, Both Ports Dese

Seite 15

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 22 of 29CapacitanceTested initially and after any design or proc

Seite 16 - [+] Feedback

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 23 of 29Switching Characteristics Over the Operating Range [20,

Seite 17

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 24 of 29Switching WaveformsFigure 5. Read/Write/Deselect Sequen

Seite 18

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 25 of 29Ordering Information Not all of the speed, package, and

Seite 19 - DLL Constraints

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 26 of 29167 CY7C1310BV18-167BZC 51-85180 165-Ball Fine Pitch Bal

Seite 20 - Operating Range

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 27 of 29Package DiagramFigure 6. 165-Ball FBGA (13 x 15 x 1.4 mm

Seite 21

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 28 of 29Document History PageDocument Title: CY7C1310BV18/CY7C19

Seite 22 - Capacitance

Document #: 38-05619 Rev. *F Revised June 2, 2008 Page 29 of 29QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress

Seite 23

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 3 of 29Logic Block Diagram (CY7C1312BV18)Logic Block Diagram (CY

Seite 24

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 4 of 29Pin Configuration The pin configuration for CY7C1310BV18,

Seite 25

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 5 of 29CY7C1312BV18 (1M x 18)1 2 3 4 5 6 7 8 9 10 11A CQ NC/144M

Seite 26

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 6 of 29Pin Definitions Pin Name IO Pin DescriptionD[x:0]Input-Sy

Seite 27 - Package Diagram

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 7 of 29CQ Echo Clock CQ Referenced with Respect to C. This is a

Seite 28

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 8 of 29Functional OverviewThe CY7C1310BV18, CY7C1910BV18, CY7C13

Seite 29 - Document History Page

CY7C1310BV18, CY7C1910BV18CY7C1312BV18, CY7C1314BV18Document #: 38-05619 Rev. *F Page 9 of 29Programmable ImpedanceAn external resistor, RQ, must be c

Verwandte Modelle: CY7C1314BV18

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Inhaltsverzeichnis

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