Cypress CY14B104M Spezifikationen PDF herunterladen

PRELIMINARY

CY14B104K/CY14B104M

4 Mbit (512K x 8/256K x 16) nvSRAM with

Real-Time-Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-07103 Rev. *I Revised June 20, 2008

Features

■ 15 ns, 20 ns, 25 ns, and 45 ns access times

■ Internally organized as 512K x 8 (CY14B104K) or 256K x 16

(CY14B104M)

■ Hands off automatic STORE on power down with only a small

capacitor

■ STORE to QuantumTrap

nonvolatile elements is initiated by

software, device pin, or AutoStore

on power down

■ RECALL to SRAM initiated by software or power up

■ High reliability

■ Infinite read, write, and recall cycles

■ 200,000 STORE cycles to QuantumTrap

■ 20 year data retention

■ Single 3V +20%, –10% operation

■ Data integrity of Cypress nvSRAM combined with full featured

Real-Time-Clock

■ Watchdog timer

■ Clock alarm with programmable interrupts

■ Capacitor or battery backup for RTC

■ Commercial and industrial temperatures

■ 44/54-pin TSOP II package

■ Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104K/CY14B104M combines a 4-Mbit

nonvolatile static RAM with a full featured real-time-clock in a

monolithic integrated circuit. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM is read and

written an infinite number of times, while independent nonvolatile

data resides in the nonvolatile elements.

The real-time-clock function provides an accurate clock with leap

year tracking and a programmable, high accuracy oscillator. The

alarm function is programmable for one time alarms or periodic

seconds, minutes, hours, or days. There is also a programmable

watchdog timer for process control.

CAP

HSB

CY14B104K

RTCcap

RTCbat

INT

BHE

BLE

Logic Block Diagram

- A

Address

DQ0 - DQ7

CY14B104M

[1]

Note

1. Address A

- A

and DQ0 - DQ7 for x8 configuration, Address A

- A

and Data DQ0 - DQ15 for x16 configuration.

[+] Feedback

1 2 3 4 5 6 ... 28 29

Inhaltsverzeichnis

Seite 1 - Real-Time-Clock

PRELIMINARYCY14B104K/CY14B104M4 Mbit (512K x 8/256K x 16) nvSRAM withReal-Time-ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose,

Seite 2

PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 10 of 29Table 3. RTC Register MapRegisterBCD Format DataFunction/RangeD7 D6 D5 D4 D3

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 11 of 29Table 4. Register Map Detail0x1FFFFTime Keeping - YearsD7 D6 D5 D4 D3 D2 D1

Seite 4

PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 12 of 290x1FFF7WatchDog TimerD7 D6 D5 D4 D3 D2 D1 D0WDS WDW WDTWDS Watchdog Strobe. S

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 13 of 29M Match. When this bit is set to 0, the seconds’ value is used in the alarm m

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 14 of 29Maximum RatingsExceeding maximum ratings may impair the useful life of thedev

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 15 of 29AC Test ConditionsInput Pulse Levels...

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 16 of 29AC Switching Characteristics ParametersDescription15 ns 20 ns 25 ns 45 nsUnit

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 17 of 29Software Controlled STORE/RECALL Cycle In the following table, the software c

Seite 10 - CY14B104K/CY14B104M

PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 18 of 29Figure 8. SRAM Read Cycle #2: CE Controlled[15, 26, 28] Figure 9. SRAM Writ

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 19 of 29Figure 10. SRAM Write Cycle #2: CE Controlled[18, 26, 27, 28]Figure 11. Aut

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 2 of 29PinoutsFigure 1. Pin Diagram - 44/54 TSOP II Pin DefinitionsPin Name IO Type

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 20 of 29Figure 12. CE Controlled Software STORE/RECALL Cycle[22] Figure 13. OE Cont

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 21 of 29Figure 14. Hardware STORE Cycle[25]Figure 15. Soft Sequence Processing[23,

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 22 of 29PART NUMBERING NOMENCLATUREOption:T - Tape & ReelBlank - Std.Speed:20 - 2

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 23 of 29Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOperating

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 24 of 2945 CY14B104K-ZS45XCT 51-85087 44-pin TSOPII CommercialCY14B104K-ZS45XIT 51-8

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 25 of 29Package Diagrams Figure 16. 44-Pin TSOP II (51-85087)MAXMIN.DIMENSION IN MM

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 26 of 29Figure 17. 54-Pin TSOP II (51-85160)Package Diagrams (continued)51-85160-**

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 27 of 29Document History PageDocument Title: CY14B104K/CY14B104M 4 Mbit (512K x 8/256

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 28 of 29*F 1890926 See ECN vsutmp8/AESAAdded Footnote 1, 2 and 3.Updated Logic Block

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Document #: 001-07103 Rev. *I Revised June 20, 2008 Page 29 of 29AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All produc

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 3 of 29Device OperationThe CY14B104K/CY14B104M nvSRAM is made up of twofunctional com

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 4 of 29The HSB signal is monitored by the system to detect if anAutoStore cycle is in

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 5 of 29Preventing AutoStoreThe AutoStore function is disabled by initiating an AutoSt

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 6 of 29Data ProtectionThe CY14B104K/CY14B104M protects data from corruptionduring low

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 7 of 29If the voltage on the backup supply (VRTCcap or VRTCbat) fallsbelow their resp

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 8 of 29.Power MonitorThe CY14B104K/CY14B104M provides a power managementscheme with p

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PRELIMINARYCY14B104K/CY14B104MDocument #: 001-07103 Rev. *I Page 9 of 29Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block