Cypress CY14B101P Spezifikationen

CY14B101P1-Mbit (128 K × 8) Serial SPI nvSRAM with Real Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 4

CY14B101PDocument Number: 001-44109 Rev. *O Page 10 of 36Write Protection and Block ProtectionCY14B101P provides features for both software and hardw

CY14B101PDocument Number: 001-44109 Rev. *O Page 11 of 36Write Disable (WRDI) InstructionWrite Disable instruction disables the write by clearing the

CY14B101PDocument Number: 001-44109 Rev. *O Page 12 of 36address (0x1FFFF) is reached, the address rolls over to 0x0000and the device continues to wr

CY14B101PDocument Number: 001-44109 Rev. *O Page 13 of 36RTC AccessCY14B101P uses 16 registers for RTC. These registers can beread out or written to

CY14B101PDocument Number: 001-44109 Rev. *O Page 14 of 36WRITE RTC (WRTC) InstructionWRITE RTC (WRTC) instruction allows the user to modify theconten

CY14B101PDocument Number: 001-44109 Rev. *O Page 15 of 36AutoStore Disable (ASDISB) instructionAutoStore is enabled by default in CY14B101P. The Auto

CY14B101PDocument Number: 001-44109 Rev. *O Page 16 of 36Real Time Clock OperationnvTIME OperationThe CY14B101P offers internal registers that cont

CY14B101PDocument Number: 001-44109 Rev. *O Page 17 of 36registers and the OSCEN bit are not affected by the ‘oscillatorfailed’ condition.The value o

CY14B101PDocument Number: 001-44109 Rev. *O Page 18 of 36flag and the hardware interrupt are both cleared when user readsthe flags register..Power Mo

CY14B101PDocument Number: 001-44109 Rev. *O Page 19 of 36Accessing the Real Time Clock through SPICY14B101P uses 16 registers for RTC. These register

CY14B101PDocument Number: 001-44109 Rev. *O Page 2 of 36ContentsPinout ...

CY14B101PDocument Number: 001-44109 Rev. *O Page 20 of 36Table 8. RTC Register Map [3, 4]RegisterBCD Format DataFunction/RangeD7 D6 D5 D4 D3 D2 D1 D

CY14B101PDocument Number: 001-44109 Rev. *O Page 21 of 36Table 9. Register Map Detail0x0FTime Keeping - YearsD7 D6 D5 D4 D3 D2 D1 D010s years YearsC

CY14B101PDocument Number: 001-44109 Rev. *O Page 22 of 360x07WatchDog TimerD7 D6 D5 D4 D3 D2 D1 D0WDS WDW WDTWDS Watchdog strobe. Setting this bit to

CY14B101PDocument Number: 001-44109 Rev. *O Page 23 of 360x02Alarm - SecondsD7 D6 D5 D4 D3 D2 D1 D0M 10s alarm seconds Alarm secondsContains the alar

CY14B101PDocument Number: 001-44109 Rev. *O Page 24 of 36Maximum RatingsExceeding maximum ratings may shorten the useful life of thedevice. These use

CY14B101PDocument Number: 001-44109 Rev. *O Page 25 of 36AC Test ConditionsInput pulse levels ... 0 V

CY14B101PDocument Number: 001-44109 Rev. *O Page 26 of 36RTC CharacteristicsOver the Operating RangeParameter Description Min Typ[13]Max UnitsVRTCbat

CY14B101PDocument Number: 001-44109 Rev. *O Page 27 of 36Switching WaveformsFigure 25. Synchronous Data Timing (Mode 0)Figure 26. HOLD TimingHI-ZVA

CY14B101PDocument Number: 001-44109 Rev. *O Page 28 of 36AutoStore or Power-Up RECALLOver the Operating RangeParameter DescriptionCY14B101PUnitMin Ma

CY14B101PDocument Number: 001-44109 Rev. *O Page 29 of 36Software Controlled STORE/RECALL CyclesOver the Operating RangeParameter DescriptionCY14B101

CY14B101PDocument Number: 001-44109 Rev. *O Page 3 of 36PinoutFigure 1. 16-pin SOIC pinoutINTWPVCAP12345678910111213NC161514VCCSOSISCKCSHSBHOLDTop V

CY14B101PDocument Number: 001-44109 Rev. *O Page 30 of 36Hardware STORE CycleOver the Operating RangeParameter DescriptionCY14B101PUnitMin MaxtPHSBHa

CY14B101PDocument Number: 001-44109 Rev. *O Page 31 of 36Ordering Code DefinitionsOrdering InformationOrdering Code Package Diagram Package Type Oper

CY14B101PDocument Number: 001-44109 Rev. *O Page 32 of 36Package DiagramFigure 33. 16-pin SOIC (0.413 × 0.299 × 0.0932 inches) Package Outline, 51-8

CY14B101PDocument Number: 001-44109 Rev. *O Page 33 of 36Acronyms Document ConventionsUnits of MeasureAcronym DescriptionBCD Binary Coded DecimalCPHA

CY14B101PDocument Number: 001-44109 Rev. *O Page 34 of 36Document History PageDocument Title: CY14B101P, 1-Mbit (128 K × 8) Serial SPI nvSRAM with Re

CY14B101PDocument Number: 001-44109 Rev. *O Page 35 of 36*E 2767333 GVCH 09/22/2009 Changed STORE cycles to QuantumTrap from 200K to 1 MillionUpdated

Document Number: 001-44109 Rev. *O Revised November 6, 2014 Page 36 of 36All products and company names mentioned in this document may be the tradema

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CY14B101PDocument Number: 001-44109 Rev. *O Page 4 of 36Device OperationCY14B101P is a 1-Mbit nvSRAM memory with integrated RTCand SPI interface. All

CY14B101PDocument Number: 001-44109 Rev. *O Page 5 of 36Figure 2 shows the proper connection of the storage capacitor(VCAP) for AutoStore operation.

CY14B101PDocument Number: 001-44109 Rev. *O Page 6 of 36Serial Peripheral InterfaceSPI OverviewThe SPI is a four-pin interface with Chip Select (CS),

CY14B101PDocument Number: 001-44109 Rev. *O Page 7 of 36SPI ModesCY14B101P device may be driven by a microcontroller with itsSPI peripheral running i

CY14B101PDocument Number: 001-44109 Rev. *O Page 8 of 36SPI Operating FeaturesPower-UpPower-up is defined as the condition when the power supply istu

CY14B101PDocument Number: 001-44109 Rev. *O Page 9 of 36Status RegisterThe Status Register bits are listed in Table 2. The StatusRegister consists of