Cypress CY7C1218H Bedienungsanleitung PDF herunterladen

1-Mbit (32K x36) Pipelined Sync SRAM

CY7C1218H

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05667 Rev. *B Revised July 6, 2006

Features

• Registered inputs and outputs for pipelined operation

• 32K × 36 common I/O architecture

• 3.3V core power supply (V

)

• 2.5V/3.3V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP

package

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1218H SRAM integrates 32K x 36 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and CE

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the Byte Write control inputs. GW

when active

LOW causes all bytes to be written.

The CY7C1218H operates from a +3.3V core power supply

while all outputs may operate either with a +2.5V or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS

ADV

CLK

BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

0, A1, A

MEMORY

ARRAY

SLEEP

CONTROL

[1:0]

,DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

BYTE

WRITE REGISTER

DQP

BYTE

WRITE DRIVER

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

DQP

DQs

Logic Block Diagram

[+] Feedback

1 2 3 4 5 6 ... 15 16

Inhaltsverzeichnis

Seite 1 - CY7C1218H

1-Mbit (32K x36) Pipelined Sync SRAMCY7C1218HCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #

Seite 2

CY7C1218HDocument #: 38-05667 Rev. *B Page 10 of 16Switching Waveforms Read Cycle Timing[17]Note: 17. On this diagram, when CE is LOW, CE1 is LOW, CE2

Seite 3

CY7C1218HDocument #: 38-05667 Rev. *B Page 11 of 16 Write Cycle Timing[17, 18]Note: 18.Full width Write can be initiated by either GW LOW; or by GW HI

Seite 4

CY7C1218HDocument #: 38-05667 Rev. *B Page 12 of 16Read/Write Cycle Timing[17, 19, 20]Notes: 19. The data bus (Q) remains in High-Z following a Write

Seite 5 - [+] Feedback

CY7C1218HDocument #: 38-05667 Rev. *B Page 13 of 16ZZ Mode Timing[21, 22]Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descrip

Seite 6

CY7C1218HDocument #: 38-05667 Rev. *B Page 14 of 16Ordering InformationNot all of the speed, package and temperature ranges are available. Please cont

Seite 7 - Maximum Ratings

CY7C1218HDocument #: 38-05667 Rev. *B Page 15 of 16© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change w

Seite 8 - AC Test Loads and Waveforms

CY7C1218HDocument #: 38-05667 Rev. *B Page 16 of 16Document History PageDocument Title: CY7C1218H 1-Mbit (32K x36) Pipelined Sync SRAMDocument Number:

Seite 9

CY7C1218HDocument #: 38-05667 Rev. *B Page 2 of 16Pin ConfigurationSelection Guide166 MHz 133 MHz UnitMaximum Access Time 3.5 4.0 nsMaximum Operating

Seite 10 - Switching Waveforms

CY7C1218HDocument #: 38-05667 Rev. *B Page 3 of 16Pin Definitions Name I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select one of

Seite 11 - (continued)

CY7C1218HDocument #: 38-05667 Rev. *B Page 4 of 16Functional OverviewAll synchronous inputs pass through input registers controlledby the rising edge

Seite 12 - Read/Write Cycle Timing

CY7C1218HDocument #: 38-05667 Rev. *B Page 5 of 16 Interleaved Burst Address Table (MODE = Floating or VDD)FirstAddressA1, A0SecondAddressA1, A0ThirdA

Seite 13 - ZZ Mode Timing

CY7C1218HDocument #: 38-05667 Rev. *B Page 6 of 16Continue Write Next L X X X H H H X Tri-State WriteContinue Write Next L H X X X H H X Tri-State Wri

Seite 14

CY7C1218HDocument #: 38-05667 Rev. *B Page 7 of 16Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not tested.)Stora

Seite 15 - Package Diagram

CY7C1218HDocument #: 38-05667 Rev. *B Page 8 of 16Capacitance[10]Parameter Description Test Conditions100 TQFP Max. UnitCIN Input Capacitance TA = 25°

Seite 16

CY7C1218HDocument #: 38-05667 Rev. *B Page 9 of 16Switching Characteristics Over the Operating Range[11, 12]Parameter Description166 MHz 133 MHzUnitMi

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