Cypress CY14B101LA Spezifikationen

STK17TA8128k X 8 AutoStore nvSRAM withReal Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Do

STK17TA8Document #: 001-52039 Rev. *C Page 10 of 24Software-Controlled STORE/RECALL CycleIn the following table, the software controlled STORE and R

STK17TA8Document #: 001-52039 Rev. *C Page 11 of 24Hardware STORE CycleFigure 12. Hardware STORE CycleSoft Sequence CommandsFigure 13. Soft Sequen

STK17TA8Document #: 001-52039 Rev. *C Page 12 of 24MODE SelectionE W G A16-A0Mode I/O Power NotesH X X X Not Selected Output High Z StandbyL H L X R

STK17TA8Document #: 001-52039 Rev. *C Page 13 of 24nvSRAM OperationThe STK17TA8 nvSRAM is made up of two functional compo-nents paired in the same p

STK17TA8Document #: 001-52039 Rev. *C Page 14 of 24atile elements. Once a STORE cycle is initiated, further memoryinputs and outputs are disabled un

STK17TA8Document #: 001-52039 Rev. *C Page 15 of 24Figure 15. Current versus Cycle TimeRTC OperationsReal Time ClockThe clock registers maintain ti

STK17TA8Document #: 001-52039 Rev. *C Page 16 of 24Calibrating The ClockThe RTC is driven by a quartz controlled oscillator with a nominalfrequency

STK17TA8Document #: 001-52039 Rev. *C Page 17 of 24InterruptsThe STK17TA8 has a Flags register, Interrupt Register, andinterrupt logic that can inte

STK17TA8Document #: 001-52039 Rev. *C Page 18 of 24RTC Register* A binary value, not a BCD value.0 - Not implemented, reserved for future use.Defaul

STK17TA8Document #: 001-52039 Rev. *C Page 19 of 24Register Map Detail0x1FFFFReal Time Clock – Years D7 D6 D5 D4 D3 D2 D1 D010s Years YearsContains

STK17TA8Document #: 001-52039 Rev. *C Page 2 of 24ContentsFeatures ...1

STK17TA8Document #: 001-52039 Rev. *C Page 20 of 240x1FFF7Watchdog TimerD7 D6 D5 D4 D3 D2 D1 D0WDS WDW WDTWDS Watchdog Strobe. Setting this bit to 1

STK17TA8Document #: 001-52039 Rev. *C Page 21 of 240x1FFF2Alarm – SecondsD7 D6 D5 D4 D3 D2 D1 D0M 10s Alarm Seconds Alarm SecondsContains the alarm

STK17TA8Document #: 001-52039 Rev. *C Page 22 of 24Ordering InformationOrdering CodesThese parts are not recommended for new designs.Packing OptionB

STK17TA8Document #: 001-52039 Rev. *C Page 23 of 24Package DiagramsFigure 17. 48-Pin SSOP (51-85061)51-85061 *D[+] Feedback Not Recommended for New

Document #: 001-52039 Rev. *C Revised April 5, 2010 Page 24 of 24All products and company names mentioned in this document are the trademarks of thei

STK17TA8Document #: 001-52039 Rev. *C Page 3 of 24PinoutsFigure 1. Pin Diagram - 48-PIn SSOPVSSA14A12A7A6DQ0DQ1VCCDQ2A3A2A1VCAPA13A8A9A11A10DQ7DQ6V

STK17TA8Document #: 001-52039 Rev. *C Page 4 of 24Absolute Maximum RatingsVoltage on Input Relative to Ground ...–0.1V to 4.1VVoltage o

STK17TA8Document #: 001-52039 Rev. *C Page 5 of 24AC Test ConditionsInput Pulse Levels ...0V to 3VI

STK17TA8Document #: 001-52039 Rev. *C Page 6 of 24RTC DC CharacteristicsFigure 4. RTC Recommended Component ConfigurationSymbol ParameterCommercial

STK17TA8Document #: 001-52039 Rev. *C Page 7 of 24SRAM READ Cycles #1 and #2Figure 5. SRAM READ Cycle #1: Address Controlled[4, 5, 7] Figure 6. SR

STK17TA8Document #: 001-52039 Rev. *C Page 8 of 24SRAM WRITE Cycles #1 and #2Figure 7. SRAM WRITE Cycle #1: W Controlled[8, 9]Figure 8. SRAM WRITE

STK17TA8Document #: 001-52039 Rev. *C Page 9 of 24AutoStore/Power Up RecallFigure 9. AutoStore/Power Up RECALLNotes10. tHRECALL starts from the tim