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CY7C1041DV33

Document #: 38-05473 Rev. *E Page 6 of 13

Data Retention Characteristics Over the Operating Range

Parameter Description Conditions

[14]

Min Max Unit

for Data Retention 2.0 V

CCDR

Data Retention Current V

= V

= 2.0V,

> V

– 0.3V,

> V

– 0.3V or V

< 0.3V

Ind’l 10 mA

Auto 15

CDR

[6]

Chip Deselect to Data Retention Time 0 ns

[15]

Operation Recovery Time t

Data Retention Waveform

3.0V3.0V

CDR

> 2V

DATA RETENTION MODE

Switching Waveforms

Figure 4. Read Cycle No. 1

[16, 17]

PREVIOUS DATA VALID DATA VALID

OHA

ADDRESS

DATA OUT

Notes

12. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of

these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.

13. The minimum write cycle time for Write Cycle No. 4 (WE

controlled, OE LOW) is the sum of t

HZWE

and t

14. No input may exceed V

+ 0.3V.

15. Full device operation requires linear V

ramp from V

to V

CC(min.)

> 50 μs or stable at V

CC(min.)

> 50 μs.

16. Device is continuously selected. OE

, CE, BHE, and BHE = V

17. WE

is HIGH for read cycle.

[+] Feedback [+] Feedback

1 2 3 4 5 6 7 8 9 10 11 12 13

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