Cypress CY62128EV30 Bedienungsanleitung PDF herunterladen (Seite 6)

CubeSat Kit PPM B1 Rev. A

August 2009 – document Rev. B

BLOCK DIAGRAM

PPM B1 provides regulated and current-limited +3.3V power, an external POR/BOR reset supervisor,

JTAG and user interfaces for programming and debugging, a provision for an external crystal, an external

high-speed

1Mbit static RAM, connections to 45 of 48 I/O pins of the PPM connector, dedicated MB

control and radio handshaking signals, a single-point analog/digital ground, and a careful assignment of

the C8051 peripherals to the PPM connector and CubeSat Kit bus. One of the C8051’s 100 pins is not

used.

VCC

+5V_USB

VCC

VCC_SD

PPM Connector

OFF_VCC

+5V_SYS

-FAULT_OC

SENSE

-RESET

DGND

AGND

LDO

+3.3V

Current-limited

switch w/protection

VCC

Reset

Supervisor

VCC

C8051F120

& debug

Program

8-pin FPC

User-fittable

crystal

6-pin FPC

JTAG

VREF0

VREFD

VREF2

P0.2/SCK

P0.5/NSS

P0.0/TX0

P0.1/RX0

P1.0/TX1

P1.1/RX1

P0.4/SIMO

P0.3/SOMI

P2.[7..0]

P3.[7..0]

XTAL

-RST

P3.7

P3.6

P3.5

P0.6

P0.7

VREF0

VREF2

IO.0

IO.1

IO.2

-CS_SD

SDO0

SDI0

SCK0 IO.3

IO.4

IO.5

IO.6

IO.7

IO.[15..8]

IO.[23..16]

VREF1

UTX0

URX0

UTX1

URX1

SCL_SYS

IO.[47..40]

AN.[7..0]

IO.[29..24]

IO.30

I0.34

IO.35

IO.36

IO.37

IO.38

IO.39

IO.[33..31]

P1.[7..2]

P0.7/SCL

P4.0

AIN0.[7..0]

DAC0

DAC1

CP1-

CP1+

CP0-

CP0+

VREF

AD.[7..0]

Latch

EMIF

VCC

ADDR[7..0]

128Kx8

Static

RAM

VCC

AD.[15..8]

-MEMBUS

MEMBANK

-RD

-WR

D.[7..0]

ALE

-MEMBUS

P5.3

P5.4

P5.5

AGND

P4.4

P4.1

P4.2

P4.3

P5.0

P5.1

P5.2

P0.6/SDA

P5.7

P5.6

P4.7/-WR

P4.6/-RD

P4.5/ALE

P7.[7..0]

P6.[7..0]

-ON_SD

-ON_MHX

-OE_MHX

-OE_USB/-INT

HS0

HS1

HS2

HS3

HS4

HS5

SDA_SYS

45ns.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

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