8-Mbit (512K x 16) Static RAMCY62157EV30 MoBL®Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 10 of 14 Truth TableCE1CE2WE OE BHE BLE Inputs/Outputs Mode PowerH X X X X X High-Z Deselect/Power
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 11 of 14Package DiagramsFigure 9. 48-Pin VFBGA (6 x 8 x 1 mm), 51-85150A1A1 CORNER0.750.75Ø0.30±0.
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 12 of 14Figure 10. 44-Pin TSOP II, 51-85087Package Diagrams (continued)51-85087-*A[+] Feedback
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 13 of 14© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subjec
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 14 of 14Document History PageDocument Title: CY62157EV30 MoBL®, 8-Mbit (512K x 16) Static RAMDocum
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 2 of 14Product Portfolio Product RangeVCC Range (V)Speed (ns)Power DissipationOperating ICC, (mA)S
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 3 of 14The following picture shows the 48-ball VFBGA pinout.[3, 4, 5]Pin Configuration (continued
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 4 of 14Maximum RatingsExceeding maximum ratings may shorten the battery life of thedevice. User gu
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 5 of 14Thermal Resistance [10]Parameter Description Test Conditions BGA TSOP I TSOP II UnitΘJATher
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 6 of 14Switching Characteristics Over the Operating Range[13, 14] Parameter Description45 ns (Ind’
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 7 of 14Switching WaveformsRead Cycle No. 1 (Address Transition Controlled)[19, 20]Figure 3. Read C
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 8 of 14Write Cycle No. 1 (WE Controlled)[18, 22, 23]Figure 5. Write Cycle No. 1Write Cycle No. 2 (
CY62157EV30 MoBL®Document #: 38-05445 Rev. *E Page 9 of 14Write Cycle No. 3 (WE Controlled, OE LOW)[23]Figure 7. Write Cycle No. 3Write Cycle No. 4 (
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