CY14B101LPRELIMINARY
Document #: 001-06400 Rev. *E Page 12 of 18
SRAM Write Cycle 1(WE
controlled)
[22, 23]
SRAM Write Cycle 2 (CE controlled)
Switching Waveforms (continued)
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Note
23. CE
or WE must be > V
IH
during address transitions.
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