Cypress CY14B101L Bedienungsanleitung PDF herunterladen (Seite 3)

CY14B101LPRELIMINARY

Document #: 001-06400 Rev. *E Page 3 of 18

Device Operation

The CY14B101L nvSRAM is made up of two functional

components paired in the same physical cell, the SRAM

memory cell and the nonvolatile QuantumTrap cell. The SRAM

memory cell operates as a standard fast static RAM. Transfer

of data can be from the SRAM to the nonvolatile cell (the

STORE operation), or from the nonvolatile cell to SRAM (the

RECALL operation). This unique architecture allows all cells

to be stored and recalled in parallel. During the STORE and

RECALL operations SRAM READ and WRITE operations are

inhibited. The CY14B101L supports infinite reads and writes

just like a typical SRAM. In addition, it provides infinite

RECALL operations from the nonvolatile cells and up to

200,000 STORE operations.

SRAM Read

The CY14B101L performs a READ cycle whenever CE and

are low while WE and HSB are high. The address specified

on pins A

0-16

determines which of the 131,072 data bytes will

be accessed. When the READ is initiated by an address

transition, the outputs will be valid after a delay of t

(READ

cycle 1). If the READ is initiated by CE

or OE, the outputs will

be valid at t

ACE

or at t

DOE

, whichever is later (READ cycle 2).

The data outputs repeatedly responds to address changes

within the t

access time without the need for transitions on

any control input pins. It remains valid until another address

change, or until CE

or OE is brought high, or WE or HSB is

brought low.

SRAM Write

A WRITE cycle is performed whenever CE and WE are low

and HSB

is high. The address inputs must be stable before

entering the WRITE cycle and must remain stable until either

CE or WE goes high at the end of the cycle.

The data on the common IO pins IO

0–7

will be written into the

memory if the data is valid t

before the end of a WE

controlled WRITE or before the end of an CE controlled

WRITE. Keep the OE

high during the entire WRITE cycle to

avoid data bus contention on common IO lines. If OE

is left low,

internal circuitry turns off the output buffers t

HZWE

after WE

goes low.

AutoStore Operation

The CY14B101L stores data to nvSRAM using one of the three

storage operations. These three operations are Hardware

Store activated by HSB, Software Store activated by an

address sequence, and AutoStore on device power down.

AutoStore operation is a unique feature of QuantumTrap

technology and is enabled by default on the CY14B101L.

During normal operation, the device draws current from V

to charge a capacitor connected to the V

CAP

pin. This stored

charge will be used by the chip to perform a single STORE

operation. If the voltage on the V

pin drops below V

SWITCH

the part automatically disconnects the V

CAP

pin from V

. A

STORE operation will be initiated with power provided by the

CAP

capacitor.

Figure 1 on page 4 shows the proper connection of the storage

capacitor (V

CAP

) for automatic store operation. Refer to the DC

Characteristics table for the size of V

CAP

. The voltage on the

CAP

pin is driven to 5V by a charge pump internal to the chip.

A pull up must be placed on WE

to hold it inactive during power

up.

To reduce unnecessary nonvolatile stores, AutoStore, and

Hardware Store operations will be ignored unless at least one

WRITE operation has taken place since the most recent

STORE or RECALL cycle. Software initiated STORE cycles

are performed regardless of whether a WRITE operation has

taken place. Monitor the HSB

signal by the system to detect if

an AutoStore cycle is in progress.

Pin Definitions

Pin Name IO Type Description

– A

Input Address Inputs used to select one of the 131,072 bytes of the nvSRAM.

DQ0 – DQ7 Input Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

WE Input Write Enable Input, Active LOW. When selected LOW, enables data on the IO pins to be written

to the address location latched by the falling edge of CE

Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.

Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read

cycles. IO pins are tri-stated on deasserting OE

high.

Ground Ground For The Device. Must be connected to ground of the system.

Power Supply Power Supply Inputs To The Device.

HSB

Input Output Hardware Store Busy (HSB). When low this output indicates a hardware store is in progress. When

pulled low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up

resistor keeps this pin HIGH if not connected. (connection optional)

CAP

Power Supply Autostore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to

nonvolatile elements.

NC No Connect No Connect. Do not connect this pin to the die.

[+] Feedback [+] Feedback

1 2 3 4 5 6 7 8 ... 18 19

Kommentare zu diesen Handbüchern

Keine Kommentare

Cypress CY14B101L Bedienungsanleitung Seite 3

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Nein Cypress CY14B101L