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Stellaris® LM3S9B96 Development Kit User’s Manual
September 5, 2010 17
A small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible by
the LM3S9B96 microcontroller. For full details on FT2232 operation, go to www.ftdichip.com.
USB to JTAG/SWD
The FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger.
A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode,
provides direction control for the bidirectional data line.
Virtual COM Port
The Virtual COM Port (VCP) allows Windows applications (such as HyperTerminal) to
communicate with UART0 on the LM3S9B96 over USB. Once the FT2232 VCP driver is installed,
Windows assigns a COM port number to the VCP channel. Table 2-4 shows the debug-related
signals.
Serial Wire Out (SWO)
The development board supports the Cortex-M3 Serial-Wire Output (SWO) trace capabilities.
Under debugger control, on-board logic can route the SWO datastream to the VCP transmit
channel. The debugger software can then decode and interpret the trace information received
from the Virtual Com Port. The normal VCP connection to UART0 is interrupted when using SWO.
Not all debuggers support SWO.
See the Stellaris LM3S9B96 Microcontroller Data Sheet for additional information on the Trace
Port Interface Unit (TPIU).
Color QVGA LCD Touch Panel
The development board features a TFT Liquid Crystal graphics display with 320 x 240 pixel
resolution. The display is protected during shipping by a thin, protective plastic film which should
be removed before use.
Features
Features of the LCD module include:
Kitronix K350QVG-V1-F display
320 x RGB x 240 dots
3.5” 262 K colors
Table 2-4. Debug-Related Signals
Microcontroller Pin Board Function Jumper Name
Pin 77 TDO/SWO JTAG data out or trace data out TDO
Pin 78 TDI JTAG data in TDI
Pin 79 TMS/SWDIO JTAG TMS or SWD data in/out TMS
Pin 80 TCK/SWCLK JTAG Clock or SWD clock TCK
Pin 26 PA0/U0RX Virtual Com port data to LM3S9B96 VCPRX
Pin 27 PA1/U0TX Virtual Com port data from LM3S9B96 VCPTX
Pin 64 RSTn System Reset RSTn
- User’s Manual 1
- Copyright 2
- Table of Contents 3
- 4 September 5, 2010 4
- List of Figures 5
- List of Tables 6
- CHAPTER 1 7
- 8 September 5, 2010 8
- September 5, 2010 9 9
- Development Kit Contents 10
- Block Diagram 11
- 12 September 5, 2010 12
- Hardware Description 13
- CHAPTER 2 13
- Clocking 14
- Power Supplies 15
- Debugging 16
- Color QVGA LCD Touch Panel 17
- Control Interface 18
- Backlight 18
- Resistive Touch Panel 18
- User Switch and LED 19
- 20 September 5, 2010 20
- Peripheral Interface (EPI) 21
- CHAPTER 3 21
- 22 September 5, 2010 22
- CHAPTER 4 23
- 24 September 5, 2010 24
- Schematics 25
- APPENDIX A 25
- Schematic page 1 26
- Schematic page 2 27
- Schematic page 3 28
- Schematic page 4 29
- SDRAM Expansion Board 30
- EPI Signal Breakout Board 30
- Schematic page 6 31
- 32 September 5, 2010 32
- Component Locations 33
- APPENDIX B 33
- 34 September 5, 2010 34
- Center Positive (+) 35
- 36 September 5, 2010 36
- APPENDIX D 37
- 40 September 5, 2010 40
- Expansion Board 41
- APPENDIX E 41
- 42 September 5, 2010 42
- Remove board 42
- Remove jumpers 42
- 44 September 5, 2010 44
- Memory Map 45
- Flash, SRAM 47
- LCD Interface 48
- LCD_DECODE CPLD 48
- APPENDIX F 49
- Installation 50
- Using the Widget Interface 53
- Register Descriptions 55
- System Control Register 56
- Interrupt Enable Register 57
- Interrupt Status Register 57
- Memory Page Register 58
- Test PadRegister 58
- LCD Control Register 58
- 60 September 5, 2010 60
- Memory Port Register 61
- Memory Window Register 61
- Installing the Software 62
- Modifying the Default Image 62
- Default FPGA Image Blocks 62
- EPI Signal Descriptions 63
- EPI, LCD, Camera I/F 66
- SRAM, Power, JTAG 67
- Tactile Switch 67
- 68 September 5, 2010 68
- APPENDIX G 69
- Male EPI expansion connector 71
- Bottom side of EM2 module 71
- 72 September 5, 2010 72
- EM2 Expansion Board 78
- References 79
- APPENDIX H 79
- 80 September 5, 2010 80
- IMPORTANT NOTICE 81
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