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Stellaris® LM3S9B96 Development Kit User’s Manual

September 5, 2010 55

This section provides the detailed register information for the FPGA expansion board.

Version Register

The Version register communicates the revision numbers of the PCB, the FPGA RTL, and the

Stellaris silicon. A dummy write of 0x0000 to this register determines if the Stellaris silicon is

revision C (or higher) and configures the EPI clocking circuit appropriately. This is required during

initialization for proper operation.

Bit Name Description

PCB Board Version:

Revision level of the FPGA expansion board.

RevC: This bit is high if the FPGA believes it is communicating with Revision C of the

silicon (or higher). This bit is only valid after being initialized as described above.

RTL Version Revision level of the code running in the FPGA expansion board.

LGML 050 [15:0] LCD Graphics Memory Address Low R/W 60

LGMH 052 [4:0] LCD Graphics Memory Address High R/W 60

LGMS 054 [11:0] LCD Graphics Memory Stride R/W 60

MPNC 056 [9:0] Memory Port Number of Columns R/W 60

MPR 058 [8:0] Memory Port Current Row R/W 60

MPC 05A [9:0] Memory Port Current Column R/W 60

MPML 05C [15:0] Memory Port Address Low R/W 60

MPMH 05E [4:0] Memory Port Address High R/W 60

MPMS 060 [11:0] Memory Port Stride R/W 60

MPORT 080 [15:0] Memory Port R/W 61

MEMWIN 400 [15:0] Memory Window R/W 61

Table F-2. Version Register

VERSION: 0xA000.0000

15 14 13 12 11 10 9 8

PCB Board Version 0 0 RevC

R R R R R R R R

76543210

RTL Major Version RTL Minor Version

R R R R R R R R

Table F-1. FPGA Expansion Board Memory Map (Continued)

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 80 81

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