Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 24)

CHAPTER 2. LAB TASK 0 - BUILD A UART IN VERILOG

2.2.2 The hardware

The system clock is running at 40 MHz. You will need a reset-signal and a send-signal,

see Figure 2.2. Both these signals are active-high.

UART

rst_i(SW1)

tx_o

rx_i

clk_i

led_o

switch_i

send_i(SW2)

Figure 2.2: The UART.

Your task is twofold:

• send an ASCII-coded character from the DIP switch to the PC by pressing the

switch SW2, see Figure 2.2.

• catch the incoming characters from rx_i and present the ASCII code on the

LED display, see Figure 2.2.

Some advice before you start:

• The signal rx_i is asynchronous. We strongly advice you to synchronize it!

• You will use your UART in lab task 1 with a slower system clock 25 MHz. We

suggest that you prepare the frequency change with an ‘ifdef ‘else ‘endif

construct.

2.2.3 A simple testbench

You will also need a test bench. Since you are designing both a transmitter and a

receiver you may choose to test them both at the same time, see Figure 2.3.

testbench

UART

clk_i

rx_i

tx_o

led_o

switch_i

send_i rst_i

Figure 2.3: A testbench.

The code for the test bench shown in Figure 2.3, is listed in Listing 2.1.

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