Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 39)

3.5. DESIGN A PERFORMANCE COUNTER MODULE

3. contain four 32 bit counters that can be read and written on the addresses 0x9900_0000

to 0x9900_000c.

4. The counter on address 0x9900_0000 shall count the number of clock cycles that

m0.cyc and m0.stb are both asserted. The counter on address 0x9900_0004

shall count the number of clock cycles that m0.ack is asserted.

5. The counter on address 0x9900_0008 shall count the number of clock cycles that

m1.cyc and m1.stb are both asserted. The counter on address 0x9900_000c

shall count the number of clock cycles that m1.ack is asserted.

6. Be aware that you will add extra signals (and counters )to this module in later

labs to measure DMA activities.

7. You may optionally use the m?.we signals to gather even more statistics.

Listing 3.2: Performance counter module port deﬁnition. The deﬁnition of the wish-

bone SystemVerilog interface can be found in the appendix, section B.5.

module p e r f _ t o p ( wishbone . s l a v e wb , w i s h b o n e . m o n i t o r m0 , m1 ) ;

re g [ 3 1 : 0 ] c t r 0 , c t r 1 ; / / yo u r c o u n t e r s

a s s i g n wb . ack = wb . s t b && wb . c y c ; / / how t o f i x t h e ack−s i g n a l

/ / y o u r co d e go e s h e r e

endmodule / / p e r f _ t o p

Laboration task 3

Design the performance counter module and use these counters to measure the per-

formance of the

dct_sw.c

program. There is also a free running timer present in the

processor. You can access it on SPR register

0x5002

. In this lab you may also use the

regular timer r egister in the processor since no operating system will modify it.

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Cypress DCT-1D Betriebsanweisung Seite 39