Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 77)

B.3. WISHBONE CLASSICAL CYCLES

B.2.6 cyc

This signal indicates that a valid bus cycle is in progress. This signal should be asserted for the

duration of all (consecutive) bus cycles.

B.2.7 ack

This acknowledgment input indicates the normal termination of a bus cycle. Abnormal termi-

nation is indicated through the err signal.

B.2.8 cti

The cti signal indicates the current bus cycle type. This signal is described in more detail in

the section on incrementing burst cycles, see section B.4.

B.2.9 bte

The cti signal indicates the current bus cycle burst type. This signal is described in more

detail in the section on incrementing burst cycles, see section B.4.

B.2.10 err

This error signal indicates the abnormal termination of a bus cycle. The behavior of the master

and slave in response to the err signal is not deﬁned in the standard.

B.3 Wishbone classical cycles

−WSS−CLK_I

ADR_O

DAT_O

DAT_I

WE_O

SEL_O

STB_O

CYC_O

VALID

ACK_I

Master signals

Figure B.2: Wishbone classical single read cycle.

A Wishbone classical bus cycle is signaled by asserting cyc and stb to the slave. These

signals are acknowledged by the ack signal from the slave. Whether to read or write can then

be selected by setting the other interface signals to appropriate levels. Fig. B.2 shows a timing

diagram for a Wishbone classical single read bus cycle. The WSS (wait state slave) signiﬁes

that the slave can insert any number of wait states by keeping the ack signal low. Fig. B.3

shows a Wishbone classical single write.

The Wishbone classical bus cycles require the entire bus cycle to ﬁnish before starting

a new cycle. This disallows bursty accesses from occupying a minimum of time since no

overlapping is allowed. This has been addressed in revision B.3 of the Wishbone standard, see

section B.4.

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Cypress DCT-1D Betriebsanweisung Seite 77