Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 35)

3.3. A SIMPLE COMPUTER

Check mon2.c to see what the monitor does at startup so that you can verify that

the hardware does the correct thing.

3.3.4 Test Your Design

In Figure 3.6a we show a test bench for the computer. The only signals that the test

bench has to activate in this case are the clk_i- and rst_i-signals. We check the

behavior of the computer by listening to tx-signal from the UART. Part of a testbench

has already been written for you in dafk_tb/lab1_tb.v. This test bench can be

started with make sim_lab1.

OR1200

I/F

Boot Monitor in ROM

RAM

Performance

Counters

Parallel Port

lab1.sv

clk_i rst_i

lab1_tb.sv

uart_tasksUARTI/F

(a) A test bench. The module uart_tasks gives a nice printout.

(b) A test run in ModelSim, showing the signals tx and rx_data in the test bench.

Figure 3.6: Simulation of your design

There is also a smaller test bench, lab1/uart_tb.sv, that will test only your

UART design. This test bench can be started with make sim_uart.

Laboration task 2

Test your computer.

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Cypress DCT-1D Betriebsanweisung Seite 35