Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 76)

APPENDIX B. THE WISHBONE SPECIFICATION

Table B.1: Wishbone signals (named from the master side).

Name Direction Width Description

adr M->S 32 Address bus

dat_o M->S 32 Data bus out

dat_i M<-S 32 Data bus in

we M->S 1 Write enable

sel M->S 4 Byte selects

stb M- >S 1 Strobe signal

cyc M->S 1 Valid bus cycle

ack M<-S 1 Bus cycle acknowledgment

cti M->S 3 Cycle type identiﬁer

bte M->S 2 Burst type extension

err M<-S 1 Bus cycle error

B.2 Interface signals

The Wishbone signals all use active-high logic (rule 2.30). Table B.1 shows a summary of the

signals in the Wishbone interface. The following subsections will describe each signal in more

detail. All signal names correspond to the master side.

B.2.1 adr

The adr signal is used to pass a binary address from the master to the slave. Note that the

address granularity is on byte level.

B.2.2 dat_o and dat_i

The dat_o signal is used to pass a binary data from the master to the slave. The dat_i signal

is used to pass a binary data from the (selected) slave to the master. The minimum granularity

of the data is byte level as selected with the sel signal.

B.2.3 we

This signal indicated whether the current bus cycles is a write or a read. The signal is asserted

for write cycles and negated for read cycles.

B.2.4 sel

The sel signal indicates where valid data is present/expected on the dat_* signals during the

current bus cycle. With byte (8-bit) granularity on a 32-bit bus this signal will have four wires.

Each wire will indicate that the corresponding byte is/should be valid.

B.2.5 stb

This signal indicates a valid data transfer cycle. The slave will assert either ack or err in

response to every assertion of this signal.

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Cypress DCT-1D Betriebsanweisung Seite 76