Cypress DCT-1D Betriebsanweisung Seite 32

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32
CHAPTER 3. LAB TASK 1 - INTERFACING TO THE WISHBONE BUS
In the return path the addressed slave’s s-bus is connected to all the masters. This
is handled by the block DEC. The ack-signal is, however, only asserted at the master
that won the arbitration.
3.3 A Simple Computer
3.3.1 General
For the lab you will have to download tsea44.tgz if you haven’t done so already.
Uncompress the zip-file to your home directory. Inspect the directory hw and you will
find:
the file lab1/lab1_uart_top.sv, a skeleton for the top file.
the file lab1.ucf, a User Constraints File.
the directory or1200 containing the CPU. The top file is or1200_top.sv.
the directory monitor containing both HW and SW for the boot monitor.
the directory wb containing the Wishbone interconnect.
the directory include containing some include files.
the directory firmware, which contains the example program dct_sw/dct_sw
that can be downloaded to your computer with the boot monitor.
3.3.2 A Wishbone Interface for the UART
Let’s start our computer design with the UART. In the introductory lab you designed a
simple UART. All that is needed now is to attach a Wishbone interface to your design,
see Figure 3.4.
Since you will use a boot monitor that is written for the standard 16550 UART,
you will want to make your design emulate that UART.
Luckily our device driver does not use much of the functionality in the 16550.
The main enhancement in the 16550 are 16 character FIFOs in both directions. This is
more or less mandatory when you run an OS, which always has some interrupt latency.
The driver routine expects three bytesized registers:
1. transmit register, adr=0, write-only
2. receive register, adr=0, read-only
3. status register, adr=5, read-only
In the status register, you will only need two F/Fs:
rx_full, set when the stop-bit is received and reset when the receive register is
read. Use signal wb_sel[3] to determine when the receive register is read.
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