Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 78)

APPENDIX B. THE WISHBONE SPECIFICATION

−WSS−CLK_I

ADR_O

DAT_O

DAT_I

WE_O

SEL_O

STB_O

CYC_O

ACK_I

VALID

Master signals

Figure B.3: Wishbone classical single write cycle.

CLK_I

ACK_I

CYC_O

STB_O

WSS

WSM

WSS

WSM

Figure B.4: Wishbone classical block cycles.

Burst-style accesses can be done t hrough the classical bus cycles. This will (almost al-

ways) require wait-states to be inserted at various points during the access. Fig. B.4 shows

a simpliﬁed timing diagram for a block (burst) access. The cyc signal indicates that a valid

bus cycle is in progress. During the bus cycle the master can respond to the acknowledgment

signal by either negating or asserting the stb signal in order to insert wait states or start new

transactions respectively.

Just as with a single read/write, the slave can keep the acknowledgment signal negated to

insert wait states if needed.

B.4 Wishbone incrementing burst cycles

So called Wishbone registered feedback bus cycles were introduced with revision B.3 of the

standard. Of these bus cycles, the Wishbone incrementing burst cycles are most useful. This

bus cycle can be used f or doing burst read accesses with high throughput because the start of a

new transaction is allowed to happen before the current transaction has ﬁnished.

The cti and bte signals indicate the type of burst cycle in progress. Table B.2 shows the

meaning of these signals

In order to keep compatibility between revisions of the standard, slaves can ignore these

signals and revert to classical bus cycles. This should give the same behavior as if the exten-

sions were not used at all.

Fig. B.5 shows a linear address burst read of four data. As can be seen the address from the

master is held constant until an acknowledgment has been received. This ensures compatibility

with the Wishbone classical cycles. After the ﬁrst data has been read the acknowledgment is

kept asserted and the data is delivered at a rate of one per cycle. This continues until the master

The 4-beat, 8-beat, and 16-beat wrap bursts mean that a set of 4, 8, or 16 addresses are repeated and

is not very useful in this lab.

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