Cypress DCT-1D Betriebsanweisung PDF herunterladen (Seite 33)

3.3. A SIMPLE COMPUTER

Control

Unit

Control

Unit

>=1 tx

send

reg

rx_full F/F

tx_empty F/F

shift

Shift

Reg

wb.stb

wb.we

wb.sel[3]

wb.dat_i[22:21]

wb.ack

wb.sel[3]

wb.we

wb.stb

wb.dat_i[16]

wb.adr[2]

end_char_tx

end_char_rx

wb.dat_o[31:24]

wb.dat_i[31:24]

shift_rx

load_tx

shift_tx

shift

load

Reg

Shift

out

load

reg

load

Figure 3.4: A sketch of the Wishbone interface for the UART. The signal load_tx is

a single-pulsed version of send. The tx_empty F/F is connected to two wires.

• tx_empty, set when the stop-bit has been transmitted and reset when the trans-

mit register is written. The 16550 has two slightly diff erent ﬂags for this case.

The monitor will work if you connect tx_empty to both these ﬂags.

Figure 3.5 shows address maps for the UART connected to an 8 bit bus and a 32 bit

bus. The transmit register should be placed on wb.dat_o[31:24], the receive register

on wb.dat_i[31:24]. The status register should be placed on wb.dat_i[23:16].

What about address decoding? The 8 most signiﬁcant bits are already decoded in the

wb.stb-signal. Since we are now using a 32 bit data bus, we will not use the two

least signiﬁcant address bits. Instead the wb.sel-signal is used to access individual

data bytes. For instance wb.sel[3] is asserted when a byte on address 0x9000_0000

or (for instance) 0x9000_0004 is accessed. To prevent an access to 0x9000_0004 to

reset the status F/Fs, we connect wb.adr[2] to the AND gates.

Preparation task 2

Why must the

wb.sel[3]

-signal be included in the reset condition for the

rx_full

F/F?

The code for the lab skeleton lab1_uart_top.sv is given in the listing 3.1. The

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 81 82

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